# Theoretical Energy Usage Loihi

Hi,
On table 2 of the Davies, et. all paper, “Loihi: A Neuromorphic Manycore Processor with On-Chip Learning,” there is a listing of simulated energy consumption on Loihi. Not being an expert on hardware design, can somebody help me determine how, given a graph, to roughly calculate projected energy usage? Ie: solve energy = f(N_neurons, N_spiking_connections, N_graded_connections, N_spikes, time_active_per_non_spiking_neuron, N_learning_rule_updates).

I see that energy linearly increases with the number of synapse updates, neuron updates, and number of spikes, but I am more fuzzy on the “tile hops” and tiles.
Thanks for your help!

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Hi Justin,

To figure this out exactly for a particular network would take considerable work, and is not something we’ve ever done. You would have to figure out how you’re mapping the network to the chip (in terms of what neurons go on what cores), and then figure out the firing rates of each neuron in your network given your input data, and exactly where each spike is being sent. (This is where the “tile hops” comes in; it’s basically the number of communication nodes that a spike has to move through to get from its source core to its target core. See Figure 2 in the paper.) You can use `nengo_loihi` to map the network to the chip for you and run it to count neuron firing rates, but it will still be some work to turn that into precise power estimates.

What would be easier is to use averages to get a rough power estimate. For example, compute the average firing rate of all neurons in your network, and make some assumptions about the average number of “tile hops” any spike would need to get from its source to its destination. For example, you could assume that neurons are randomly distributed across cores, and thus the average tile hops would be the average number of nodes between two randomly chosen cores. You would need to know roughly how the cores are laid out on a chip (i.e. the dimensions of the mesh); this might be in the paper somewhere. Since tile hops have a low power cost, I wouldn’t worry too much about having a great estimate for the number of tile hops.

Thank you! That is really helpful.
I had another question regarding how well suited Loihi is for analyzing the affect of graded potentials. Can potentials that are graded as opposed to all or none be used as part of a learning rule for Loihi? And if so, is there any information regarding the energy consumption of graded potentials?

I’m not familiar with the idea of graded potentials. Based on some quick reading, I believe all incoming potentials to a neuron are graded on Loihi, since they’re scaled by synaptic weights.

As for learning, Loihi learning rules can either be based directly on spikes or on activity traces (filtered spike trains). I do not know what it would mean to include graded potentials in here. One way you can make the learning more flexible is by using custom C code running on the chip to set or modify these activity traces. This is what we do for our PES learning rule. However, I’m pretty sure this is not more energy efficient because rather than happening right in a core (as the spike based learning rules do), it involves communication with one of the general x86 processors that are available on the chip.

Unfortunately, none of this is currently supported by `nengo_loihi`. The only learning rule we currently support is the PES learning rule.

Thank you very much!