Hi @xchoo, thank you!
My aims for the system include making the hardware portable to many different FPGA architectures, sizes, and boards, so the hardware is written in SystemVerilog and is heavily parametrised so that the memory usage can be finely controlled.
A rundown of the existing backend’s codebase would be very useful, thank you! I have had a look through the codebase and I would like to determine the best way to interface my current implementation with Nengo.
The scope that I am eventually aiming for is for full models to be deployed onto dev boards for use in robotics, edge applications, etc. with no host needed. The aspect that I would like to implement first before developing an interface to Nengo is to expand the ensemble dimensionality; the example code only has one dimension (A clarification of how higher dimensions are implemented at a low level would also be very helpful!) After that, I would like to deploy one ensemble as a first step, then expand to full models and add learning rules.
The communication with the host computer is done via USB UART at the moment, with a Verilog UART on the FPGA and the Pyserial library on the host. This was done as many FPGA dev boards have USB serial capability, increasing portability. It runs at around 2Mb/s, but a ‘hat’ for my dev board (Alchitry Au) allows higher data rates over USB-C, which could be an option for other boards too. At the moment, only the input/output values of the system is transferred, but I would like to add debug information/spike addresses/etc.
At the moment, the board is programmed by compiling the parameters from the constructed model into a binary memory file by a compiler I’ve written in Python, and then are baked into the bitstream when the synthesis tools run; this is to allow for full optimisation of all the data paths to reduce the model’s memory footprint on the FPGA’s fabric.
Thank you very much for your help, I’m looking forward to developing this system further!